1. Field of the Invention
The present invention relates to a method for detecting a resistive path to ground or a predetermined potential in electronic non-volatile memory devices that comprise at least one sectored array of memory cells.
2. Description of the Related Art
As it is well known, a faulty condition known as the “erase fail”, on the occurrence of which at least one memory sector can no longer be erased, has grown to be a major problem with last-generation flash memories.
This faulty condition is determined by the way an erase operation, the so-called channel erasing, is carried out.
More particularly, it is known to erase all the cells of a whole sector of a flash memory array by applying a suitable voltage to the control terminals of the memory cells.
FIG. 1 shows, schematically and to an enlarged scale, a portion of a semiconductor integrated circuit, which is fabricated conventionally to a flash memory cell 4. In particular, this portion 1 comprises a substrate 2 doped with a first dopant that may be of the P type. The substrate 2 serves the whole wafer where the portion 1 is also formed.
Preferably, a three-well structure, including an intermediate well 3 and an innermost well 5 in which the flash memory cell 4 is integrated, is preferably formed in the substrate 2.
Actually, all the cells 4 of a given sector of the flash memory array are formed in the innermost well 5. The well 5 is also doped with the first dopant of the P type, and a source region 6 and a drain region 7 of the cell 4 are formed towards its surface. These regions are islands of a second type of dopants that may be of the N type.
A thin layer of tunnel oxide separates the surface of the well 5 from a floating gate region 8, the latter being separated from a control gate region 9 by means of an isolation layer 10, which is usually an interpoly oxide 10, also called ONO layer.
The cell 4 is connected to first or positive and second or negative charge pump circuits 11 and 12, respectively.
During an erase operation, the innermost well 5 is applied a predetermined positive voltage value by means of the first or positive charge pump circuit 11. The value of this positive voltage usually reaches +8V, and is also applied to the floating gate region 8. The control gate region 9, on the other hand, is brought to a negative voltage value that reaches −9V by means of the second charge pump circuit 12.
In FIG. 1 this situation is schematically shown, in the form of paths illustrating the application of the above voltage values.
In this situation, the voltage across the interpoly oxide layer 10 may rise to a value equal to 17V and exceed it.
Where weak points occur in the structure of the interpoly oxide layer 10, the layer is apt to deteriorate and even to break. When it does, the second or negative charge pump circuit 12 becomes shorted to the first or positive charge pump circuit 11 while the cell 4 is erased, as indicated in FIG. 2 by the conduction path 13.
A net outcome is that one or more cells in the sector affected by the short-circuit in well 5 is not erased, thus bringing the memory to an erase-fail state.
The prior art already proposes a way to overcome this problem that consists of applying a field redundance concept in the erase algorithm, with attendant sector redundance.
More particularly, this prior proposal consists of replacing a failed memory element, or even a whole memory sector, with a new element. The erase algorithm is suitably modified, so to have the erase operation performed on the redundant sectors and not on the failed sectors anymore.
Furthermore, the redundance operation would be available through the service life of a memory device on the market, as well as to the test procedures for factory testing memory devices before delivery.
In particular, in the course of an erase operation, a check phase is performed, which allows to divert the erase operation to a “sparing” sector in the event of sector failing and thus to properly erase such a sector.
Of course, this can only be accomplished if one or more redundant sectors are available to replace the failed ones. Thus, the main shortcoming of the above prior proposal is that each device must be equipped with a whole redundant sector even if only one cell in the failed sector actually requires replacement.
It should be noted in this respect that the average size of a flash memory sector is 1 Mbit, and that erase fails are frequent occurrences. Thus, it would be necessary to use a large number of sectors having large dimensions to effectively correct faulty devices. On the contrary, replacing memory cell sectors bodily is a comparatively simple matter, although heavily restrictive of circuit area: it is merely necessary to arrange for the address of a sector found failed to be “shifted” to a redundant sector each time that the failed sector is addressed.
Heretofore, the state of the art has provided no practical solution to the problem of readily detecting memory cells in an erase fail condition, this being a condition that may indeed occur during an erase phase and is largely unpredictable, with no simple way of detecting the failed cells.